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Anna Kiran

IP Logic Design Engineer, Intel, Malaysia

Anna Sai Kiran is an experienced professional with over 7 years of expertise in Design Verification, specializing in PCIe Sub-System Verification as of 2021.

Having a background in Master of Technology (M.Tech.) in VLSI & CE from IIIT Hyderabad and Bachelor of Technology (B.Tech.) in ECE from Vardhaman College Of Engineering, Anna has a strong educational foundation.

Throughout her career, Anna has held challenging roles such as ASIC Engineer at NVIDIA, Design Engineer I at Wafer Space, and Design Engineer at Vitesse Semiconductor, where she played a vital role in understanding Design Architecture, developing testbench components, creating tests, and checkers for multiple protocols.

Anna's project involvement includes working on various protocols like PCIe, Ethernet, AXI-ST, AXI-Lite, NV Switch XBAR, MAC, and MACSEC projects, showcasing her diverse skill set in design verification.

Her accomplishments extend to validating PCIe Gen4 IP at gate-level simulation with timing annotation, demonstrating her technical proficiency and attention to detail.

With a strong foundation in education and a wealth of experience in leading design verification projects, Anna Sai Kiran is a valuable asset in the field of semiconductor and VLSI design.

Anna Kiran
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Location

India