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Anupam Rastogi

Design Verification Manager at Facebook

Anupam Rastogi is a seasoned professional with a proven track record in leading and managing large verification teams for complex FPGA / SoCs from concept to production.

He has extensive experience in building and leading large verification teams for FPGA / SoC projects, as well as managing, mentoring, and leading large offsite teams.

Anupam is KPI-driven, focusing on quality and customer feature priority sensitivity, with the ability to make unbiased decisions aligning with the company's strategic goals.

His expertise includes working effectively with software, architecture, and silicon teams to manage priorities and expectations for successful project outcomes.

Anupam Rastogi is a strong advocate of structured verification methodologies, emphasizing reuse across verification / FPGA and silicon platforms.

He is skilled in constraint random, self-checking test benches, test plans/reviews, and coverage-driven closure, with hands-on experience in unit level and full chip verification using UVM / OVM methodologies.

Additionally, he has specialized knowledge in video codecs (H264 / HEVC), PAN WiFi, video processing, and full chip architectures.

Anupam's technical skills encompass Verilog, C/C++, PERL, SystemVerilog, SystemVerilog Assertions & UVM / OVM, system design (Boards / PCB, Lab debug, Assembly / C based diagnostics), and familiarity with CAD tools such as NC Verilog, SimVision, and Questa.

He pursued his Bachelor Of Technology at Birla Institute Of Technology, Mesra, and has held key positions in reputable organizations including Director Verification at Esencia Technologies Inc., GigPeak, Inc., and Magnum Semiconductor.

Anupam Rastogi has also served as a Senior Manager - Verification, Consultant - Backend Video Verification, Verification Lead, Engineering Manager - Verification at various companies such as Ozmo Devices, Philips Semiconductors, and OPTI Inc.

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Location

Sunnyvale, California