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Ares Tahiraga

European Master in Embedded Computing Systems

Ares Tahiraga is a Research Assistant at the University of Kaiserslautern (Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau) in Germany. His professional experience includes roles such as a student assistant at the university since February 2021 and a working student at LUBIS EDA since August 2022. He also has prior experience as a software developer at Communication Progress from February 2019 to January 2020.24

Ares has contributed to research in embedded systems and computer architecture, as demonstrated by his co-authorship of a paper titled "A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems," presented at the MBMV 2024 workshop in Kaiserslautern, Germany.1 Additionally, he has been involved in collaborative projects like the ISOLDE project, which focuses on advancements in system design and verification.3

His LinkedIn profile username is "ares-tahiraga-08b2ba17a," where further details about his academic and professional background can be found.2

Highlights

Oct 29 · kluedo.ub.rptu.de
[PDF] Advanced Methods for Model-Driven Safety Analysis and Verification
Feb 14 · portal.fis.tum.de
A Comparative Analysis of ARM and RISC-V ISAs for Deeply ...
ISOLDE |

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Ares Tahiraga
Ares Tahiraga, photo 1
Ares Tahiraga, photo 2
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Albania