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Divya Kadiyala

Graduate Research Student

Divya Kadiyala is a graduate research student at Georgia Institute of Technology, specializing in Hardware Transactional Memory Systems with a focus on mitigating spurious capacity aborts in on-chip caches and buffering structures under the guidance of Dr. Alexandros Daglis.

Before her current role, Divya worked at Cadence Design Systems in San Jose, CA as a Sr. Applications Engineer, where she specialized in implementing power sign-off solutions for memory macros, ASIC, and SOCs. Her responsibilities included working on IR & EM power sign-off tools, collaborating with R&D and product engineering teams, and developing flow methodologies and features for the Voltus® power sign-off tool, particularly focused on power-grid abstraction and its correlation with SPICE results.

During her time at Arizona State University, Divya worked as a student research aide at the VLSI Research Lab, contributing to the TC25 research project by conducting tests on TC25 SRAM memory arrays, collecting and analyzing data from fabricated test chips, and co-authoring two IEEE journal publications.

Divya's technical skills include proficiency in languages like C, C++, Tcl, Tk, and Perl, experience with simulators such as SESC and gem5, and expertise in Hardware Description Languages like SystemVerilog and Verilog. She is also well-versed in EDA tools including Cadence Voltus IR & EM analysis tools, Cadence Encounter SOC implementation tool, Synopsis DC compiler & VCS, Hspice, and Cadence Spectre.

In addition to her academic pursuits, Divya has held various internships and positions at organizations like Samsung Semiconductor, Luminous Computing, and Tata Consultancy Services, showcasing a well-rounded professional background in both corporate and research environments.

Divya Kadiyala
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Location

Atlanta, Georgia, United States