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Kee-Hian Tan

Kee-Hian Tan is a distinguished professional with extensive experience in various fields. He is currently a Director of Analog Design at AMD, a position he has held since June 2020.1 In this role, he focuses on high-speed 112Gb/sec Serdes design for FPGA.1

Prior to his current position, Tan had a notable career progression:

  1. Senior Analog Design Manager at Xilinx (June 2015 - June 2020)1
  2. Analog Design Manager at Xilinx (September 2012 - June 2015)1
  3. Staff Analog IC Design Engineer at LSI Logic (October 2009 - August 2012)1
  4. Analog IC Design Engineer at Marvell (March 2001 - September 2009)1

Tan's educational background includes:

  • BEng and MEng in Electrical Engineering from the National University of Singapore (1996 - 2000)1
  • '0' and 'A' Levels from Raffles Institution/Junior College (1988 - 1993)1

During his academic years, Tan achieved impressive accolades, including three Dean's List appearances, one Vice Chancellor's List, and First Class honors.1 He was also the top student nationwide for O levels and achieved straight As in A Levels.1

Tan's expertise lies in analog design, particularly in high-speed and wide-band applications. His work has involved various aspects of analog IC design, including ADC, wideband LNA, high-speed write drivers, and low noise biasing circuits.1

Related Questions

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Kee-Hian Tan
Kee-Hian Tan, photo 1
Kee-Hian Tan, photo 2
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Location

Singapore