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Nathan Kistner

Senior ASIC Floorplan Design Engineer at NVIDIA

Nathan Kistner is a seasoned Physical Design Engineer with a strong focus on driving optimization in the physical design/integration flow and methodologies at the macro and chip levels.

He is proficient in tasks such as floorplanning, place and route, clocking, and timing closure, along with building automation scripts to streamline the design process.

Nathan has a Bachelor of Science in Electrical and Computer Engineering from the University of Rochester, where he also gained valuable experience as a Project Assistant, Undergraduate Intern, Workshop Leader, and Teacher's Assistant.

Throughout his career, Nathan has held key roles at renowned organizations such as NVIDIA, NASA Jet Propulsion Laboratory, Intel Corporation, and IBM, contributing significantly to ASIC floorplan design, physical design, hardware characterization, and integration.

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Location

Los Angeles Metropolitan Area