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Pankaj Deshmukh

Staff ASIC Design Engineer at Qualcomm

Pankaj Deshmukh is a seasoned professional with expertise in designing for performance focusing on power management techniques. He has a strong background in architecting synchronous and asynchronous designs, particularly in the 16FF/20soc & 28nm technology domains. Pankaj is well-versed in high-speed digital design (> 4Gbps), low power design, and silicon debug and testing.

His specialties include proficiency in tools like Verilog, Synopsys Design Compiler, RTL Power, and more for comprehensive gate-level power analysis. He is also skilled in Cadence tools (Virtuoso), SPICE, Cacti, SimpleScalar, as well as programming languages such as C, Perl scripting, and assembly language. Pankaj has hands-on experience with lab hardware tools including oscilloscopes, spectrum analyzers, and digital meters.

Pankaj Deshmukh pursued a Bachelor of Engineering in Electronics at the Department of Technology, Savitribai Phule Pune University, and furthered his education by obtaining a Master of Science in Computer Engineering from the University of Southern California.

In terms of professional experience, Pankaj has held key roles at Qualcomm, where he worked as a Staff ASIC Design Engineer. He has also served as a Senior ASIC and PHY Design Engineer at Qualcomm, showcasing his expertise in the semiconductor industry. Additionally, he has a background as a Grading Assistant at the University of Southern California and as a Research Associate at Evalueserve.

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Location

San Diego, California