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Shilpa Sathyanarayana

Shilpa Sathyanarayana is a seasoned professional with over a decade of experience specializing in Standard Cell and IO Cell Characterization. Her expertise lies in the development of NLDM, CCS, ECSM liberty models, and the validation of Standard Cell and IO Cell libraries. Shilpa has a strong background in creating Cell library views, including Timing, Power, and Noise models, as well as power grid views and library exchange formats necessary for Digital Implementation flow. She has demonstrated complete ownership of the entire cell library development process and has successfully mentored junior team members to enhance their skill sets. Additionally, Shilpa is well-versed in IBIS modeling for various types of IO cells, encompassing full chip IBIS modeling. She possesses proficiency in Power and Rail Analysis of Digital blocks and comprehensively understands the impact of a package on Rail analysis of Digital blocks. Shilpa excels in both block-level and chip-level static timing analysis (STA) and has hands-on experience in block-level Spice simulations using Spectre circuit simulator.

Shilpa Sathyanarayana
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Location

Bangalore Urban, Karnataka, India