Sign In

Somanath Maddala

SoC Design Engineer at Intel Corporation

Somanath Maddala is a proficient SoC level Verification Engineer with 4 years of professional experience in functional and gate level verification, specializing in power aware gate level simulations.

His expertise includes verifying reset release, initialization sequences, boot-up procedures, and X behavior in simulations. Somanath also excels in supporting debugging for multiple core related functions like directed-tests, stalls, and assertions.

He holds a Master of Science (MS) degree from Portland State University and a Bachelor's degree with First Class with Distinction from Jawaharlal Nehru Technological University.

Somanath has worked in various esteemed organizations including Intel Corporation where he served as a SoC Design Engineer. He has also been associated with Intel Corporation as a Graduate Technical Intern, Portland State University as a Graduate Teaching Assistant and Student Technician, AMD as a Contingent Worker-Verification Engineer, Soctronics as a Design Engineer 1, VEDAIIT for Diploma in Logic Design, and Moschip Semiconductor as an Intern.

Somanath Maddala
Add to my network

Location

Portland, Oregon, United States