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Joel Emer
Senior Distinguished Research Scientist at Nvidia
Joel Emer is a prominent figure in computer architecture and engineering with a distinguished career spanning academia and industry. Here are some key details about him:
Professional Roles
- Senior Distinguished Research Scientist at Nvidia, where he explores future architectures and develops modeling and analysis methodologies.13
- Professor of the Practice at MIT's Electrical Engineering and Computer Science Department (EECS).12
- Member of MIT's Computer Science and Artificial Intelligence Laboratory (CSAIL).23
Educational Background
- Ph.D. in Electrical Engineering from the University of Illinois in 1979.12
- M.S. in Electrical Engineering from Purdue University in 1975.12
- B.S. in Electrical Engineering from Purdue University in 1974, with highest honors.12
Research Contributions
Dr. Emer has made significant contributions to various areas of computer architecture, including:
- Processor microarchitecture for VAX, Alpha, and X86 processors.2
- Development of quantitative approaches to processor performance evaluation.23
- Advancements in simultaneous multi-threading technology.2
- Analysis of architectural impacts of soft errors.2
- Memory dependence prediction and cache organization.2
- Spatial architectures and accelerator designs for deep learning.23
Achievements and Recognition
- Fellow of both ACM and IEEE.1
- Recipient of the 2009 Eckert-Mauchly Award for lifetime contributions in computer architecture.1
- Holder of over 25 patents and author of more than 60 papers.2
- Recipient of the 2023 B. Ramakrishna Rau Award.4
Previous Work Experience
Before joining Nvidia, Dr. Emer worked at Intel as an Intel Fellow and Director of Microarchitecture Research. He also held positions at Compaq and Digital Equipment Corporation (DEC).2
Joel Emer's extensive experience and contributions have made him a highly respected figure in the field of computer architecture and engineering.
Highlights
A couple months ago, I was very honored to have been the recipient of the Bob Rau award for my contributions to computer architecture. A video of my acceptance speech given at the MICRO conference in Toronto was recently posted to YouTube; https://lnkd.in/eSmD32iS.
After a long time in development, we are excited to announce that our book titled "Efficient Processing of Deep Neural Networks" is now available for pre-order. The book is scheduled for publication in May 2020:
https://lnkd.in/eRU64BV
This book aims to provide a structured treatment of the key principles and techniques for enabling efficient processing of deep neural networks (DNNs). The book covers background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of the DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as a formalization and organization of key concepts from contemporary works that strives to provide insights that may spark new ideas.
Co-authors: Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang
#deepneuralnetworks #dnn #deeplearning #machinelearning #artificialintelligence #computerarchitecture #book #architectures #tutorial #computerchips #accelerators #morganclaypool
